FPGA Prototyping of Single-Polarization 112-Gb/s Transceiver for Optical Multilevel Signaling With Intensity and Delay Detection

As the proof-of-concept of a next-generation 100-Gb/s/channel high-speed optical transceiver for short- to mid-range applications, we develop a first full-rate and fully-functional FPGA-based single-polarization 16APSK/16QAM transceiver prototype using optical delay- and intensity-detection. Almost all the major transceiver functions, such as multilevel modulation/demodulation, timing recovery, framing functions with FEC, and linear equalizers are implemented into eight FPGAs, and the feasibility of the proposed transceiver with small circuit size and low power consumption is confirmed. Various compensation functions previously reported for the performance improvement of the delay-detection-based multilevel signaling, such as Rx-side phase noise, chromatic dispersion canceling circuits, compensation of unbalance of balanced photodetectors, symbol decision with non-Euclidian metric, etc., are also implemented in the real-time transceiver for the first time. In this paper, its basic concept, FPGA implementation, real-time signal demodulation, and BER performances are shown and four-channel WDM (448 Gb/s) field trial over 18.2-km SMF is also demonstrated.