Reliability degradation in the scope of aging — From physical to system level

Advances in technology have paved the way for making embedded on-chip systems ubiquitous in our daily life. Unfortunately, compared to previous generations, the current nano-CMOS era introduces reliability challenges at an increased pace. As a matter of fact, technology scaling is reaching its limits where certain aspects endanger the correct functionality of hardware/software on-chip systems. They have been enumerated by the International Technology Roadmap for Semiconductors (ITRS). Of these aspects, aging effects are at the forefront and thus there is an indispensable need to increase the reliability of on-chip systems with respect to them. Despite the fact that aging effects originate from the physical level, they are spatially and temporally driven by the running workloads at the system level. Importantly, aging effects may propagate through different levels, from the physical all the way up to the system level, to ultimately have a deleterious impact there and degrade the reliability of the entire system. Therefore, investigating the aging-induced reliability degradations from the physical level to system level is inevitable.