Dynamic Quaternary Circuit with Neuron-MOS Transistor

A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some other favorable properties including the less complex structure, full logic swing, low propagation delay and no static power consumption. All the proposed circuits are verified by HSPICE simulation results with TSMC 0.35µm 2-ploy 4-metal CMOS technology.