Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling

Spiraling costs of a product revision demand that we mitigate risks to product yield due to unintended disconnects between SPICE models used for design and production silicon, and intentional process retargeting for product performance optimization. This often necessitates product robustness to about +/-4.0-sigmas or about 60 ppm. However, the computational costs of even the most advanced simulation techniques are so prohibitive for many of the large circuit design problems that one often cannot obtain visibility to circuit behavior below about 5000 ppm. In this paper, we build on the scaled sigma sampling (SSS) foundation presented earlier and develop a formalism for efficient assessment of circuit yield exposure to low probability tails, including estimation of its confidence interval and optimization of process sigma scale factors and sample sizes used for the SPICE simulations. We illustrate the efficacy of SSS through an extended suite of circuit yield estimation examples including one that investigates the yield dependencies of a normality capable metric on process shifts and multiplicity.