A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multicore-Based Parallel Embedded Systems*

This chapter presents a novel, queueing theory-based modeling technique for evaluating multicore embedded architectures that do not require architectural-level benchmark simulation. This modeling technique enables quick and inexpensive architectural evaluation, with respect to design time and resources, as compared to developing and/or using existing multicore simulators and running benchmarks on these simulators. Based on a preliminary evaluation using the models, architectural designers can run targeted benchmarks to verify the performance characteristics of selected multicore architectures. The chapter proposes a method to quantify computing requirements of real benchmarks probabilistically. The modeling technique provides performance evaluation for workloads with any computing requirements as opposed to simulation-driven architectural evaluation that can provide performance results for specific benchmarks. The queueing theoretic modeling approach can be used for performance per watt and performance per unit area characterizations of multicore embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.