Partial reconfiguration and specialized circuitry for flexible FPGA-based packet processing

In order to process network packets at high rates, network functions like routing or firewalling require specialized hardware like TCAMs (Ternary Content Addressable Memories), ASICs (Application Specific Integrated Circuits), or GPUs (Graphics Processing Units). Such hardware must be fast enough to process packets at line rate, and furthermore, it must be programmable in order to update the packet processing policy (e. g., a forwarding table or firewall rule set). From a fundamental point of view, though, these goals are conflicting because a generic programmable circuit must provide sufficient resources to support a wide range of policies, which can lead to unused circuitry and low clock rates. In addition, it misses logic optimization opportunities with regard to the structure of the installed policy. In this work, we investigate the optimization potential of automatically generated network processing circuits that are tailor-made for a specific policy. Using the example of router forwarding information bases (FIBs), we demonstrate that circuits which are partially evaluated with respect to the implemented FIB need more than one order of magnitude less logic resources than an equivalent generic forwarding circuit. We combine this approach with the partial reconfiguration capability of FPGAs in order to obtain an efficient low-latency forwarding engine whose matching circuitry can be replaced on demand.