Interconnect modeling of global metals for 40nm node

This paper presented a proposed interconnect model for the system-on-chip (SoC) wire dimension estimation and planning. The proposed model utilized Wong-Lee-Ma (WLM) capacitance equation and generated new fitting coefficients to each global metal layer through least-square curve fitting method using the 40nm capacitance samples from the foundry's datasheet. Benchmarking with the interconnect layout circuit (ILC), the proposed model attained good accuracy with respect to WLM equation in estimating the average propagation delay in each global metal layers 6 and 7 having an average delay percentage error of only 1.58% with 700 um metal length and 2.63% with 1000 um metal length, respectively. The proposed model has effectively predicted the interconnect resistance and capacitance to represent the characteristics of interconnect metal when simulated for propagation delay. The model and the method presented will be implemented for 40nm global metals that would be used for SoC pre-design wire dimension estimation and planning.