Real-time performance of FPGA-based MMC valves for HVDC systems

Simulation tools are necessary to research and develop modular multi-level converter (MMC) based HVDC systems for the future power grid. Real-time simulators offer the ability to connect to real physical equipment in a hardware-in-loop (HIL) scheme to test and design controllers, protection systems and encompass the complete operation and response of an HVDC system. The complexity of an MMC valve poses challenges for real-time modelling. For the RTDS Simulator, a surrogate network topology is used to model MMC valves to reduce the computational requirements of the valve model but still maintain the accuracy of a real valve. To model up to 512 submodules (SMs) per valve at a time-step as small as 2.5 μsec, Field Programmable Gated Array (FPGA) are used to compute the MMC valve model and is interfaced to the main RTDS hardware. To demonstrate the performance and accuracy of the FPGA-based MMC valve model, comparison results are provided between the RTDS and PSCAD simulation of a point-to-point link for AC and DC faults.