Characterization of thermal vias for 3D ICs using FEM analysis

3D stacking of microprocessors is an idea that promises to continue the accomplishment of high performance processors while allowing the increment of transistors density inside a given area. However, 3D stacking inevitably increases the power density and, therefore, thermal issues related to this idea must be overcome first in order to make use of all the advantages of 3D processors. In literature, the use of vertical thermal vias has been suggested to mitigate this problem because they facilitate the heat transfer between the layers, however assuming that can be located anywhere in the chip. Therefore, in this paper we propose and investigate the use of localized thermal vias. They are inserted into dedicated silicon areas between cores, in which power is not dissipated. In general, without vias, the heat would flow vertically to the heat sink, almost uniformly in the entire chip. With thermal via region, the impact is clearly visible: although no power is dissipated in this region, a significant amount of heat passes through it.