Out-of-plane NML modeling and architectural exploration

One of the most innovative solutions studied as an alternative technology to CMOS transistors is represented by NanoMagnetic Logic (NML). It exhibits remarkable characteristics that overcome some intrinsic limitations of CMOS as low power consumption and the possibility to merge logic and memory in the same device. We present the design of a full adder entirely based on single domain out-of-plane nanomagnetic logic (pNML). We propose different solutions of the same circuit which allow us to obtain the best performance in terms of occupied area and timing. We modeled, using VHDL (VHSIC Hardware Description Language), the pNML basic elements and then we performed micromagnetic simulations to demonstrate the correct operation of the circuits.