Physical design optimizations for a high-resolution third-order sigma-delta modulator

A 3rd-order single-bit sigma-delta modulator is designed using TSMC 0.35-µm 2P4M process, which achieves a 97-dB SNR in a signal bandwidth of 20 kHz and with a sampling frequency of 5.12 MHz. The modulator is implemented by a fully-differential switched-capacitor CIFB architecture, which possesses two separate paths for realizing different coefficients, and the original DAC in the feedback path is implemented by one of them. Considering of circuit performance, physical design optimizations such as matching, noise shielding, latch-up prevention for internal circuits, and the construction of internal ESD protection structure are employed. At the same time, it also deals with the problems that designers are not able to take care of at work. The result shows that a perfect performance consistency with only 8-dB loss is attained.