S-CFG: a representation model for system synthesis

A representation model (S-CFG, system control flow graph) for system specification and synthesis is described, which is organized in two levels (block and thread). The management of the control/data flow information is performed through the use of control/data flow graphs owning: 1) hierarchical definition of control edges, 2) suitable management of timing constraints through timing edges, 3) definition of data communication through data edges. The use of hierarchy in control edges makes it possible to define in a powerful and compact way the execution semantics of the S-CFG.