Performance estimation of data-flow applications for IP-based system design

This paper addresses the problem of performance estimation for data-flow algorithms, and proposes a novel approach suitable in IP-based design methodology. It assumes that an algorithm is defined as a set of interacting blocks, where each block is associated with implementations for target processors, and the delay for each implementation has been already measured and is characterized by a delay equation. The estimation is performed using delay equations, rather than considering detailed implementations of the blocks. This assumption matches well with the trend of system design, in which the system behavior is specified by using already characterized components. The estimation procedure takes into account decisions made carefully at compile time, such as inter-block scheduling and static memory allocation. This estimation technique is very fast and accurate, in particular for algorithms with small run-time dependencies such as those in data-flow applications. The procedure has been implemented, and preliminary experimental results are presented for single DSP architectures to demonstrate its effectiveness.