Analysis of an efficient partial product reduction technique

In this paper, an efficient method of partial product reduction is analysed. there are a number of techniques for partial product reduction it can be use of Wallace and Dadda schemes or can be use of compressor. Here we have studied a number of techniques for partial product reduction and came to a conclusion that compressors are better among them and we have inserted a concept of sleep transistor in order to further improve their designing. Compressor is an important part of multiplier as the maximum space in multiplication process is taken by partial products these are used to reduce the space equipped by partial products. The compressor architecture given in this paper are designed using three-level MCML gates, which are required one for improvement in speed, power consumption and area. Another concept of sleep transistor is combined with this compressor which is useful in reducing the leakage current. Designing is done in a 16nm TSMH CMOS tehnology using Tanner EDA 14.1 v tool.