Damascene-gate thin film transistors with ultra-thin gate dielectrics

Summary form only given. The push towards larger and higher resolution flat panel displays requires an improvement in current thin-film transistor (TFT) performance. Devices should have lower threshold voltages, sub-threshold slopes and, in particular, lower gate line resistances if large, high-resolution, video quality displays are to be realized. This can be achieved by using thicker gate lines and thinner gate dielectrics. However, since amorphous silicon TFTs currently being used in active-matrix liquid crystal displays are bottom-gate structures, there is the problem of step coverage. Specifically, a thick gate dielectric is required to adequately cover the gate metal in order to prevent leakage current between the gate and the source/drain. The approach presented in this paper is to embed the gate metal into a trench made into a silicon nitride passivating layer above the substrate so that the top of the gate metal is level with the surface of the passivating layer. This damascene-gate structure has several advantages.