I. Introduction
Traditionally, time-dependent dielectric break-down (TDDB) as a critical part of technology qualification reliability mechanisms is limited by the lifetime of the worst performing chips population among all shipped chips, i.e., the low-percentile population of a Weibull lifetime distribution. The worst performing chips have to survive a certain set of operating conditions and lifetime target (e.g., <100 ppm failure rate at 1 V for 10 years). However, the wafers selected for constant voltage stress (CVS) test generally will not come from the worst performing group fabricated in a production line. In order to characterize the worst performing group of chips, some special-built wafers using the via-shifted process were fabricated for TDDB CVS test [1]. The drawbacks here are the unrealistic defects induced by such skewed process, and out of normal geometry variations due to such subground rule features.