A Realistic Method for Time-Dependent Dielectric Breakdown Reliability Analysis for Advanced Technology Node

This paper proposes a methodology to determine a realistic time-dependent dielectric breakdown failure rate. The in-die constant voltage stress was performed to determine the chip level Weibull shape (β_die) and voltage acceleration factor, while a voltage ramp (Vramp) is performed in production line (inline Vramp) to determine the via-to-line and line-to-line spacing distributions. We found that for the chip population with spacing (s) smaller than 4 nm, the in-die voltage accelerations based on power-law and sqrt-V models do not lead to a significant difference in the lifetime prediction. For the chips with large spacing, the stress voltage (~20 V) is significantly higher than the operating voltage (1 V). The extrapolation using the power law results in an infinitely long lifetime, which could lead to an overoptimistic reliability prediction. In this paper, a new method is introduced for a more realistic failure rate calculation, which is the superposition of the failure rates of chips with small spacing (s <; 4 nm) and the failure rates of chips with large spacing, by using different voltage acceleration models.