Complementary Floating Gate Transistors With Memristive Operation Mode

A two-terminal complementary floating gate transistor architecture with a memristive operation mode is proposed. Therefore, a diode configuration wiring scheme is assumed for n-channel metal–oxide–semiconductor and p-channel metal–oxide–semiconductor-based floating gate transistors (MemFlash), which enables the persistent device resistance to be varied according to the history of the charge flow. By means of a capacitive device model, we show that the n-channelMemFlash cells exhibits bipolar resistive switching from high-to-low resistance state, while the p-channel MemFlash cells switches complementary to the n-channel type under drain–source voltage application. By combining both memristive cells to a single two-terminal device structure, a complementary resistive switching device is obtained (C-MemFlash) with a bipolar, symmetric switching characteristics, and an increased number of end-resistant states. This allows realizing a rich variety of memory and logic functionalities for new nanoelectronic concepts.