Substrate resistance modeling and circuit-level simulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress

In CMOS technologies, the layout and placement of devices and substrate contacts can have significant impact on the circuit's ESD (electrostatic discharge) performance due to their interactions through the common silicon substrate. To perform accurate circuit-level ESD simulation, a circuit model for the silicon substrate is needed. In this work, we propose a new substrate resistance network model. In addition, we provide a novel and accurate substrate resistance extractor iSREX (Illinois substrate resistance extractor) using the 3D finite difference method. It takes into account the three-dimensional effects of the vertical substrate doping profile and the substrate contact placement. The usefulness of the proposed model and the resistance extractor for layout optimization is demonstrated with a case study.