A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS

This work presents the design and implementation of a fully integrated broadband medium power stacked amplifier in 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack to increase the output voltage swing along with the output impedance. The load impedance is further optimized with a resistive feedback which not only results in broadband operation but also avoids a lossy broadband output matching network which reduces area significantly. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier shows a measured peak saturated output power from 13 dBm to 8.5 dBm and a P1dB of 7 dBm to 4 dBm from 0.3 GHz to 10 GHz. The measured gain is 9 dB with a gain ripple of ±1.5 dB in the entire frequency range, yielding a fractional bandwidth of 188%. The measured load-pull -1 dB, -2 dB output power contours verify the optimum impedance around 50 Ω. The active chip area is only 0.44mm
²
.