A high-level DRAM timing, power and area exploration tool

In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Evaluating the impact of DRAM design decisions therefore requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload which requires a full system simulator, running a complete software stack. In this paper, we introduce DRAMSpec, an open source high-level DRAM bank modeling tool. As major contribution, we move the DRAM modeling abstraction level from detailed circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications and use cases. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row buffer size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16% DRAM performance improvement and 13% DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures for which no datasheets are available.

I. Introduction

Dynamic random access memories (DRAMs) account for a significant share of any system's power and energy consumption, be it battery-driven mobile devices or high-performance computing servers [1], [3]. To meet the increasing demands, DRAM architects apply different techniques to provide higher bandwidth and reduce latency [2]. However, the performance improvements come at the cost of larger die sizes, and increases in the overall power consumption of DRAMs. Balancing these trade-offs is therefore key.