Flat-Topology High-Throughput Compute Node With AWGR-Based Optical-Interconnects

This study presents simulation studies on the execution time and energy consumption of optical multi-socket boards with on-chip, all-to-all, and contention-less arrayed waveguide grating routers-based interconnection. This study considers throughput and energy-efficiency optimizations based on dynamic voltage and frequency scaling under realistic, shared memory, and cache-coherent PARSEC benchmarking traffic. The benchmark results show how a low-latency, optical inter-socket interconnection can provide significant execution time reduction, and up to 3× energy savings when using dynamic variable bandwidth communication techniques when compared to an electronic baseline. The proposed architecture can be used as “building block” for future energy-aware large-scale systems.