A Scaling-Friendly Low-Power Small-Area $\Delta\Sigma$ ADC With VCO-Based Integrator and Intrinsic Mismatch Shaping Capability

This paper presents a first-order scaling-friendly VCO-based closed-loop ΔΣ ADC. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly OTAs and precision comparators. It arranges two VCOs in a differential manner, which cancels out even-order distortions. Most importantly, it has an inherit mismatch shaping capability that automatically addresses the DAC mismatches. The prototype ΔΣ ADC in 130 nm CMOS occupies a small area of only 0.03 mm
²
and achieves 66.5 dB SNDR over 2 MHz BW while sampling at 300 MHz and consuming 1.8 mW from a 1.2 V power supply. It can also operate with a low analog supply of 0.7 V and achieves 65.8 dB SNDR while consuming 1.1 mW.