Characterization of the immunity of integrated circuits (ICs) at wafer level

This paper deals with the characterization of the immunity of integrated circuits (ICs) by means of their susceptibility to conducted radio frequency (RF) electromagnetic interferences (EMI). It describes and analyses a framework to perform such characterization at wafer level, highlighting the benefits that are reaped from it and the problems that can be faced during the test bench setup and the measurement procedure, providing some possible solutions.