Requirements and constraints for the design of smart photodetector arrays for page-oriented optical memories

We discuss the feasibility of smart photodetector arrays (SPDAs) as the optoelectronic interface in page-oriented optical memory systems. In contrast to charge-coupled device arrays, SPDA's can combine fast parallel access with some processing capabilities, such as data decoding and error control. We develop a framework for SPDA design by defining their operational requirements and by delineating their scalability constraints with respect to pixel complexity, electrical power dissipation, and optical power limits. In the case of volume holographic memories, the low-diffraction efficiency of photorefractive crystals will ultimately determine page size, while for other storage technologies the primary constraint will be the circuit complexity. We also present our implementation of an experimental SPDA designed to perform parallel error correction on an entire page of data and satisfy the sustained data rates of parallel optical memories. Our prototype, fabricated in 0.35-/spl mu/m complementary metal-oxide-semiconductor, integrates a differential photoreceiver with a cluster error correction code capable of achieving corrected output data rates scalable to hundreds of gigabits-per-second in the current technology.