GPU acceleration for PCA-based statistical static timing analysis

Timing analysis is one of the most widely used techniques in digital IC designs. It is increasingly over-loaded by growing circuit sizes and complexities arising from nanometer VLSI technologies. One well-known challenge is process variations, which need to be addressed in timing analysis at least by considering different process corners. Adaptive circuit design, a promising technique for handling variations, further needs statistical static timing analysis (SSTA), which is much more time consuming than variation-oblivious timing analysis. This work explores GPU (Graphic Processing Unit) based parallel computing techniques for accelerating SSTA. Previous works on GPU acceleration are mostly for Monte Carlo based SSTA. By contrast, we focus on SSTA using PCA (Principal Component Analysis), which is intrinsically more efficient. We develop a new batch-based task scheduling algorithm and investigate other speedup techniques such as latency hiding. Experiments are performed on ISPD'13 benchmark suite, which has circuits of over 100K gates. Compared to sequential SSTA, our approach can achieve the identical timing results with average speedup of 22X and 134X on conventional circuits and adaptive circuits, respectively. Our approach is also compared with GPU-based Monte Carlo SSTA and obtains 39X speedup with 0.77% error on timing yield estimation.