A 200-MSPS 6-bit flash ADC in 0.6-/spl mu/m CMOS

This paper describes a 6-bit flash analog-to-digital converter (ADC) which performs the sampling function in a partial-response, maximum-likelihood (PRML) disk drive read channel. It operates with sampling frequencies up to 200 MSPS and achieves an effective number of bits (ENOB) of 5.5 bits with F/sub in/=50 MHz and 5.0 bits at F/sub in/=100 MHz. It consumes 380 mW at 5 V and occupies 2.7 mm/sup 2/. Other features include a bit-error rate of <1e-10 and a programmable nonlinear transfer function.