Standard ternary inverter based on junction leakage-enhanced nanoscale planar CMOS and its variation immunity

We propose a novel standard ternary inverter (STI) based on nanoscale planar CMOS technology for a compact design of multi-valued logic (MVL). By enhancing junction band-to-band tunneling (BTBT) leakage with high channel doping for STI operation, the “third” intermediate state (V
_INT
) can be successfully obtained at V
_DD
/2 in the conventional binary CMOS inverter. It is demonstrated that the variability of the intermediate level (ΔV
_INT
<;80mV) can be allowable into the worst noise margin (>0.1V).