Performance degradation due to thicker physical layer of high k oxide in ultra-scaled MOSFETs and mitigation through electrostatics design

In scaling the dimensions of transistors, gate oxide thicknesses are also scaled. Thinning SiO
₂
as gate oxide causes gate tunneling. In order to prevent the tunneling, high k dielectric have been used in place of SiO
₂
. Using a thicker dielectric for the same equivalent oxide thickness (EOT) as SiO
₂
has a negative effect on the device performance through impacting 2D electrostatics. In this work, the effects of high k on double gate (DG) and silicon-on-insulator (SOI) devices are studied. It has been found that using high k for the same EOT can drastically drop the device performance for SOI and DG MOSFETs, with more pronounced degradation for SOI. Also, in thinning the channel thickness, the impact of oxide k variation can be reduced.