On the Automated Verification of User-defined MBIST Algorithms

As the complexity of system-on-chips increases, verification of their self-test structures becomes a major bottleneck in the design cycle. The emergence of programmable memory BISTs that support user-defined test algorithms offer high flexibility at the expense of complexity and vulnerability to errors. The traditional approach to ensure that a design meets its functional requirements is based on large automatically generated testbenches, but it falls short of comprehensive semantic verification for user-defined test algorithms, which remains a very tedious task that often has to be performed manually. This paper presents a methodology to bridge that gap of automation. The proposed approach generates a sequence of memory commands from a high-level test algorithm specification and compares them against the actually applied signals at the memory. It supports different types of memory blocks and various test algorithms in combination with algorithmic stresses. Additionally, it also greatly facilitates the debugging of incorrectly implemented test algorithms.