Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

Since the beginning of study of the Secure Hash function (SHA), it has been thoroughly studied by designers with the goal of reducing the area, frequency, and throughput of the hardware implementation of this cryptosystem. The Secure Hash function algorithm has become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and Blake-256 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieve good performance in term of area, frequency and throughput.