A high linearity, image/LO-rejection I/Q up-conversion mixer for 5G cellular communications

A high linearity, high image/LO-rejection in-phase/quadrature (I/Q) direct up-conversion mixer for 5G cellular communications is designed and implemented in 65nm CMOS. The proposed chip is implemented with quadrature LO generator and LO buffer amplifiers, and employs a complementary derivative superposition (DS) technique with pre-distortion for high linearity. The symmetric layout enhances the image/LO-rejection. The proposed mixer achieves the output 1-dB compression point of 2dBm and output third-order intercept point of 15.7dBm at 27.6GHz while consumes 15mW from 1V power supply. The measured conversion gain is 11.4dB and the measured image rejection ratio and LO leakage are −61dBc and −56dBc, respectively.