A 0.015-mm$^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

This brief illustrates the design of an inductorless high-speed clock generator. Compared to inductance-capacitance (LC) oscillators, ring oscillators are used in order to achieve a wide frequency-tuning range with a small chip area. By employing a cascaded phase-locked loop (PLL) architecture, the phase noise of the oscillator can be effectively suppressed. The first PLL is implemented with high-voltage devices under 1.8-V supply to provide a clean reference for the second PLL. The second PLL consists of only low-voltage devices, with a supply voltage of 0.9 V for high-speed operation. Following the second PLL, a clock doubler multiplies the PLL output clock by a factor of 2, which avoids power-consuming high-frequency clock dividers. In order to minimize any mismatch effects, special layout techniques are employed for the second voltage-controlled oscillator and the clock doubler. The prototype chip was fabricated in 28-nm complementary metal oxide semiconductor (CMOS) technology, and it occupies an active area of only 0.015 mm
²
. The proposed PLL achieves a maximum output frequency of 32 GHz and consumes a total power of 30 mW, exhibiting a power efficiency of 0.9 mW/GHz.