Chip design of a 12-bit 5MS/s fully differential SAR ADC with resistor-capacitor array DAC technique for wireless application

A 1.8-V 12-bit 5MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. To reduce DAC switching energy and chip area, a hybrid resistor-capacitor DAC is applied. To save energy, asynchronous control logic to drive the ADC is used. A pre-amplifier based comparator circuit is built to reduce the kickback noise from the dynamic latch designs. With 1.8 V supply voltage and 5.0 MHz sampling rate, measured results achieve -0.55/0.72 LSB (Least Significant Bit) of DNL (differential nonlinearity) and -0.78/0.92 LSB of integral nonlinearity (INL) respectively, and 10.76 bits of an effective number of bits (ENOB) at 1MHz input frequency. The chip area is 0.83 mm
²
including pads and the power consumption is 490μW for optical and wireless communications.