A 312GHz antenna array receiver in 65nm CMOS utilizing self-oscillating 3X subharmonic mixer frontend

A 312GHz antenna array receiver is presented in this paper. The receiver is a double-conversion superheterodyne architecture. The first down-conversion is accomplished by a self-oscillating 3X subharmonic mixer frontend, and the second down-conversion is performed by a Gilbert-cell mixer and an LO. The receiver is co-designed and integrated with a 4-element loop antenna array. By mixing an RF input signal at 312 GHz with the 3
^rd
harmonic of the 96 GHz LO, the first IF of 24 GHz is produced (f
_IF1
=f
_RF
-3f
_LO1
). The second LO is at frequency of 22.3 GHz, and the second IF is 1.7 GHz (f
_IF2
=f
_IF1
-f
_LO2
). The antenna array receiver exhibits a measured conversion loss of 19 dB from 312GHz RF to 1.7GHz IF, and has a -3dB bandwidth of 1.2 GHz. It is implemented in 65nm CMOS. The chip occupies an area of 1.71 mm
²
and consumes DC power of 110 mW.