Tunneling FET device technologies using III-V and Ge materials

A important challenge of tunneling field-effect transistors (TFETs) is to realize both low SS of sub-60 mV/dec. and high drain I
on
/I
off
ratio at the same time [1, 2], which strongly demands the optimization of materials, structures and fabrication process. For this purpose, the choice of source/channel materials with the reduced (effective) band gap is important for increasing tunneling current with suppressing off current. Thus, we are currently focusing planar-type TFETs using Ge/III-V and their hetero-structures. The critical issues and challenges of these TFETs are summarized in Fig. 1. One of the key issues is the formation of the steep and high quality source junctions, which provide both high tunneling current and low off current. Fig. 2 shows two types of planar TFETs, which we are currently studying. One is an in-situ doping p
⁺
Ge source/strained Si (sSi) channel TFETs [3, 4], composed of the type-II hetero-structure shown in Fig. 3. The other is an InGaAs TFET with Zn-diffused p
⁺
source junctions [5, 6].