Signal propagation on seamless high off-chip connectivity (SHOCC) interconnects

Placing long on-chip signal lines in an interconnect substrate is regarded as a solution for the long lossy line (L/sup 3/) problem (Davidson et al, 1998). Modeling and simulation of SHOCC signal interconnects are described here. Simulations were carried out using a low impedance ideal driver and cascaded CMOS drivers to drive SHOCC interconnects and also typical on-chip interconnects so that a comparative study of their electrical performance could be made.