Can Homojunction Tunnel FETs Scale Below 10 nm?

The main promise of tunnel FETs (TFETs) is to enable supply voltage (V
_DD
) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing V
_DD
and channel length (L
_ch
) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high-performance TFET with both low V
_DD
(~0.2 V) and small L
_ch
(~6 nm). In this letter, it is shown that scaling TFETs in general requires scaling down the bandgap Eg and scaling up the effective mass m* for high performance. Quantitatively, a channel material with an optimized bandgap (E
_g
~ 1.2qV
_DD
[eV]) and an engineered effective mass (m*
^-1
~ 40V
_DD
^2.5
[m
₀
^-1
]) makes both V
_DD
and L
_ch
scaling feasible with the scaling rule of L
_ch
/V
_DD
= 30 nm/V for L
_ch
from 15 to 6 nm and the corresponding V
_DD
from 0.5 to 0.2 V.