Implementation and Modeling for High-performance I/O Hub Used in SPARC M7 Processor-Based Servers

The I/O Hub (IOH) for SPARC M7 processor-based servers is an ASIC providing high performance, flexible, and virtualized access to multiple Gen3 PCIe devices. The IOH's top-level interconnect, connecting multiple PCIe Root Complexes to a set of SPARC M7 protocol interface units, proved challenging for design, verification, performance modeling, and physical implementation. Close collaboration between these disciplines was required to deliver a production quality ASIC. We report on some specific technical issues we encountered and how the interconnect design strategy shifted through the course of development as we made optimizations based on performance modeling feedback and physical design constraints.