Technology and design of GaN power devices

This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron (<10%) is obtained, both at room temperature and at high temperature.