FPGA implementation of delay optimized single precision floating point multiplier

Multiplication of floating point numbers found extensive use in DSP applications involving huge range. The critical part in floating point multiplication is the multiplication of mantissas which uses 24∗24 bit integer multiplier for single precision floating point numbers. The speed of the system can be enhanced by improving the speed of multiplication. In this paper a 24 bit Vedic multiplier has been proposed using 3∗3 Vedic multiplier as its basic block. This paper proposes a IEEE-754 single precision floating point multiplier which handles over flow, under flow and rounding. The proposed and conventional floating point multipliers based on Vedic mathematics are coded in Verilog, Synthesized and simulated in ISE Simulator. It is implemented on iWave Systems Unified Learning Kit (ULK), which is Spartan6 family xc6slx25t-2fgg484 FPGA. Maximum combinational path delay and number of slices required on FPGA are compared for proposed and conventional multipliers. The results clearly indicate that proposed method have a great impact on improving the speed and reduce the area required on Spartan 6 FPGA.