Fault tolerant system for FPGA using simulation based fault injection technique

Field Programmable Gate Array (FPGA) devices provide high capability in implementing complicated system. The downside of this technology is that it is vulnerable to radiation, and this sensitivity will increase with technology scaling. The improvement of single-event upsets (SEUs) throughout standard or sensible redundancy may be an ancient approach for turning out with fault-tolerant systems; on the other hand, even in several redundant systems, SEUs can lead to system failure if they occur at identical time. We have a tendency to work with a run-time reconfiguration strategy to beat failures caused by unidirectional SEUs occurring at identical time in every forefront and surplus module. The planned style is collection of addition tiles containing computation cells and equivalent hot-spares. The variety of fault injection technique exists but, we find that the simulation-based fault injection way is best suited for SRAM as it provides the maximum amount of controllability and observability. As a result, the planned fault tolerant system uses the simulation primarily based fault injection technique so as to inject SEU at intervals the configuration memory.