FPGA design for decimeter scale integration (DMSI)

Creating large area FPGAs is limited by defective sections and the maximum reticule print size (/spl sim/3/spl times/3 cm). FPGAs are well suited for expanding into monolithic multiprint systems 2 to 9 times larger (5-10 cm square) we call deciMeter scale integration (DMSI). DMSI expands system capacity, while producing many copies per wafer. Its design criteria is much simpler than the complex wafer scale integration, but still uses defect avoidance routing around flawed blocks to build complete working systems. FPGAs have the main features required for successful DMSI systems: a repeatable cell, built in switchable flexible routing, high connectivity requirements between cell blocks, and flexibility with many potential applications. Modest changes at the periphery of FPGAs chips enables DMSI capability. Laser formed connections and cuts have proven effectiveness in bypassing fabrication time defects and creating defect free working wafer scale systems. The important DMSI criteria for laser defect avoidance is that defect free devices should need no correction. Depending on the DMSI size and current chip yields design defect avoidance requirements vary from simple row column substitution to cell by cell/row column substitution with redundant signal paths. Power shorts defects and how they are handled prove an important limitation on chip size.