Design and performance measurements of an FPGA accelerator for a 100Gbps wireless data link layer

To achieve 100Gbps wireless transmission, not only a very fast physical layer is required. The effort of the analog transceiver can be wasted due to the overhead induced by the higher network layers. Delays and latencies caused by a duplex switching can dramatically reduce the goodput of the link. In every microsecond of a delay, 12.5kB of the data transfer is wasted. Therefore, we need to extend the frame size, but that will lead to a higher packet error rate.