Automation of FPGA performance monitoring and debugging Using IP-XACT and graph-grammars

Divide and conquer is already a proven strategy to handle the complexity of state-of-the-art SoCs. For any minor or major revision of an SoC, difficult decisions about its architecture have to be made at very early stages of the design cycle. System prototyping on FPGAs is an essential step in the SoC design flow for the verification of the hardware architecture. In this paper, we present a graph-grammar-based methodology to automate the FPGA prototyping for SoC performance monitoring and debugging analysis. Our work uses the IP-XACT description of vendor-specific hardware monitoring and debugging IPs for the target FPGA platform. Using graph-grammar principles the hardware monitors (HM) are automatically integrated into the host SoC architecture under consideration. Under the FPGA resource constraints, our tool splits the set of analysis tasks into multiple subsets, with each subset fitting into the available FPGA resources. The tool solves this as a classical bin packing problem. The tool then generates the SoC IP-XACT descriptions and the design descriptions for FPGA programming with integrated HMs for each new subset. The new SoCs are functionally equivalent to the original SoC.