Radix-2r arithmetic for FIR filter design optimization

Finite impulse response (FIR) filtering is an ubiquitous operation in digital signal processing systems. It is generally implemented in full-custom style due to the high-speed and low-power design requirements. The hardware design of a FIR filter is mainly dominated by the multiplier block, which is generally implemented as a network of adders, subtractors and shifters for more efficiency in speed and power. In a recent work, a fully predictable and sublinear runtime heuristic for the multiplication by a constant has been developed. It is called RADIX-2
^r
. In this paper, RADIX-2
^r
is applied to the FIR filter design optimization. In comparison to the existing heuristics, RADIX-2
^r
exhibits the shortest adder-depth, leading therefore to the best results in speed and power.