Design of current-controlled current conveyor stage with systematic current offset reduction

This contribution presents modification of current-controlled current conveyor (CCCII) designed in order to reduce the systematic DC current offset of transfer between X and Z terminal and also an example of practical design including practical guideline and recommendations. Simulations in Cadence Spectre simulator with ON Semiconductor/AMIS I2T100 based on 0.7 μm technology CMOS07 were provided for verification of discussed features.