Clock synchronization technology based on FPGA

To solve clock synchronization problem in distributed system, two hardware methods were introduced. External 1PPS clock was used to generate synchronized clock (S clock) in local frequency domain. In one method, 1PPS clock was directly tracked and locked by hardware logic, and then stimulates S clock immediately. 1PPS glitch and clock-lost problems in field were solved. In the other method, the multi-clocks mathematical models were built to correct 1PPS clock self-jitter. All the program were realized in one FPGA chip with NiosII soft CPU, which were pure physical layer synchronization style. Compared to traditional software solutions in the host computer, hardware clock synchronization can reach microseconds precision, and is more stable.