Low On-Resistance Normally-Off GaN Double-Channel Metal–Oxide–Semiconductor High-Electron-Mobility Transistor

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with
$V_{\mathrm {th}}$
of +0.5 V at
$I_{\mathrm {DS}}= 10 ~\mu \text{A}$
/mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm
²
/(
$\text{V}\cdot \text{s}$
). The on-resistance is as small as 6.9
$\Omega \cdot \text {mm}$
for a DC-MOS-HEMT with
$L_{G}/L_{\mathrm {GS}}/L_{\mathrm {GD}} = 1.5/2/15~\mu \text{m}$
, and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained.