An Improved Successive-approximation Register Design For Use In Monolithic A/D Converters

An improved design for a successive-approximation register (SAR) for use in A/D converters is presented. The proposed design is suitable for 12L imple mentation such that a definite savings in devices is obtained over previous designs using the separate sequencer and code register approach. This par ticular design scheme operates in a fully synchro-nous mode with the clock allowing a reduction in propagation delay to be realized.