Hardware based analysis of RFID anti-collision protocols based on the standard EPCglobal Class-1 Generation-2

Radio Frequency Identification (RFID) technology is undergoing a remarkable development in the last few years. In this technology, identification information is exchanged between two devices: readers and tags. If two tags attempt to transmit simultaneously, a collision is produced. This phenomena, known as the tag collision problem, is becoming increasingly important, since it leads to an increase in the number of reader transmitted bits and identification delay, in addition to a wastage of energy and bandwidth. In this context, protocols based on the EPCglobal Class-1 Generation-2 (EPC C1G2) standard arbitrate collisions by adjusting the transmission frame size. The standard presents an uncertainty in the selection of the frame size, since it does not specify the exact value. This has led to many different alternatives. This paper presents a hardware analysis of the most relevant anti-collision protocols which deal with this uncertainty. The focus of this analysis is to design and evaluate with VHDL the tag's chip design in order to extract the number clock cycles a tag employs to be identified.